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turning off instruction and data prefetch on A53

DougM

We are trying to turn off the speculative prefetch on an the A53 cores in an LS1043A.

We are using the LS1043Ardb reference board running uboot.

We can find the cache enable/disable/flush functions, but nothing that configures the prefetch on L1 or L2.

Any ideas?

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    I am able to control some of the data prefetching wit the CPUACTLR_EL1 register, as suggested below.

    However we are still seeing some speculative instruction behavior that appears to be erratic.

    If I run the same code several times, I see an instruction fetch pattern that will be different by one or several instruction fetches.

    We think it has something to do with the branch prediction.

    So, we are wondering if there is a way to wither disable/clear/set/reset the branch prediction in the A53?

    We are thinking there might be a scenario we could run to at least ensure that the table is in a known state.

    Thanks,

    Doug

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  • 0

    I am able to control some of the data prefetching wit the CPUACTLR_EL1 register, as suggested below.

    However we are still seeing some speculative instruction behavior that appears to be erratic.

    If I run the same code several times, I see an instruction fetch pattern that will be different by one or several instruction fetches.

    We think it has something to do with the branch prediction.

    So, we are wondering if there is a way to wither disable/clear/set/reset the branch prediction in the A53?

    We are thinking there might be a scenario we could run to at least ensure that the table is in a known state.

    Thanks,

    Doug

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