We are trying to turn off the speculative prefetch on an the A53 cores in an LS1043A.
We are using the LS1043Ardb reference board running uboot.
We can find the cache enable/disable/flush functions, but nothing that configures the prefetch on L1 or L2.
Any ideas?
Hi DougM,
The CPUACTLR_EL1 register provides some control on the prefetch.
Best regards,
Vincent.
Hi Vstehle,
Thanks for the response.
In the uboot code for the ls1043sRDB, there is a README.core_prefetch file that has a note in it to not turn off prefetch on cpu0, as it might produce unknown results.
Do you know what that is about?
We are running in a scenario where we would be willing to trade some speed optimization for a little more determinism. The processor doesn’t always prefetch the same way based on local criteria that we have no control over.
Thanks in advance,
Doug
from A53 CPU point of view, there is no problem regarding prefetch, you could have a look at A53 errata document https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d?token=
The L1 cache prefetch can be disabled by setting CPUACTLR.L1PCTL to 0b000.
For determinism, you might preload the date to cache with cache prefetch instructions.
I am able to control some of the data prefetching wit the CPUACTLR_EL1 register, as suggested below.
However we are still seeing some speculative instruction behavior that appears to be erratic.
If I run the same code several times, I see an instruction fetch pattern that will be different by one or several instruction fetches.
We think it has something to do with the branch prediction.
So, we are wondering if there is a way to wither disable/clear/set/reset the branch prediction in the A53?
We are thinking there might be a scenario we could run to at least ensure that the table is in a known state.
Thanks,