We are trying to turn off the speculative prefetch on an the A53 cores in an LS1043A.
We are using the LS1043Ardb reference board running uboot.
We can find the cache enable/disable/flush functions, but nothing that configures the prefetch on L1 or L2.
Any ideas?
from A53 CPU point of view, there is no problem regarding prefetch, you could have a look at A53 errata document https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d?token=
The L1 cache prefetch can be disabled by setting CPUACTLR.L1PCTL to 0b000.
For determinism, you might preload the date to cache with cache prefetch instructions.