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Hi,
I am facing "Bus error on memory operation" while executing below instruction while invalidating and flushing the TLB.
I am not able to understand what is the reason for "Bus error" as it is a TLB operation instruction ? Also what Bus error signify ?
Also similar error is coming while I try to invalidate instruction cache.
/* Invalidate and flush the TLB */
"tlbi alle2 \n\t" \
Thanks,
TCR_ELn.T0SZ sets the size of the virtual address space described by the tables pointed at by TTBR0_ELn. That is, the address space will go from 0x0000,0000,0000,0000 to X. The maximum size of the address space is 48 bits, which would make X=0x0000,FFFF,FFFF,FFFF.
The way it is encoded is: Size of Address Space (in bits) = 64 - T0SZ
Examples:
48-bit address space (X=0x0000,FFFF,FFFF,FFFF): T0SZ = 16
40-bit address space (X=0x0000,00FF,FFFF,FFFF): T0SZ = 24
32-bit address space (X=0x0000,0000,FFFF,FFFF): T0SZ = 32
The size of the address and the granule size together set the starting level of translation. Each level of translation describes different sized blocks of address space, the sizes varying based on the granule selected. For example, for 4K granule:
Level 0: Each entry represents 512GB of address space
Level 1: Each entry represents 1GB of address space
Level 2: Each entry represents 2MB of address space
Level 3: Each entry represents 4KB of address space
So if, using T0SZ, you shrink the total address space to 512GB or less - you don't need a L0 table. Starting level would L1.
Similarly, if you shrink the address to 1GB or below, you don't need a L1 table. Starting level would L2.
The same theory applies the other granules, it's just the sizes are different.
The ARM ARM gives tables that tell you the starting level of translation for different address sizes and granules: Table D4-10, Table D4-13 and Table D4-16.
NOTE: There is an extra setting for 2nd stage translation, but as you referred to TTBR0_EL2 (which controls stage 1) I haven't gone into that.
Forgot to mention....
This begs the question of what happens if you set T0SZ to 0, which would make the address space larger than the allowed maximum. From the ARM ARM:
The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 then it is IMPLEMENTATION DEFINED whether: • The implementation behaves as if the field were programmed to 16 for all purposes other than reading back the value of the field. • Any use of the TxSZ value generates a stage 1 Level 0 Translation fault.
The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 then it is IMPLEMENTATION DEFINED whether:
• The implementation behaves as if the field were programmed to 16 for all purposes other than reading back the value of the field.
• Any use of the TxSZ value generates a stage 1 Level 0 Translation fault.