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How to remap the vector table in an A9 core

prahsman

I'm having an issue/misunderstanding on remapping the vector table for an A9 core in a bare metal (flat mapped) application. I assumed I could create a vector table in some arbitrary location in RAM, load that location into the vbar register:

ldr r0, =vector_tbl
mcr p15, 0, r0, c12, c0, 0 //write VBAR register

and when an interrupt occurred (via the gic/IRQ), control would pass to the IRQ handler. This isn't happening. Control actually passes to the svc handler with the cpu in IRQ mode. I'm pretty sure this is a result of not remapping the vector table correctly. Any guidance on this?

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  • 0 in reply to prahsman

    ARMv7AR Manual:

    B4.1.156   VBAR, Vector Base Address Register, Security Extensions

    ...


    Vector_Base_Address, bits[31:5]  
    Bits[31:5] of the base address of the low exception vectors. Bits[4:0] of an exception vector is the
    exception offset, see Table B1-3 on page B1-1166.
    Bits[4:0]  Reserved, UNK/SBZP.

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  • 0 in reply to prahsman

    ARMv7AR Manual:

    B4.1.156   VBAR, Vector Base Address Register, Security Extensions

    ...


    Vector_Base_Address, bits[31:5]  
    Bits[31:5] of the base address of the low exception vectors. Bits[4:0] of an exception vector is the
    exception offset, see Table B1-3 on page B1-1166.
    Bits[4:0]  Reserved, UNK/SBZP.

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