I'm having an issue/misunderstanding on remapping the vector table for an A9 core in a bare metal (flat mapped) application. I assumed I could create a vector table in some arbitrary location in RAM, load that location into the vbar register:
ldr r0, =vector_tbl mcr p15, 0, r0, c12, c0, 0 //write VBAR register
and when an interrupt occurred (via the gic/IRQ), control would pass to the IRQ handler. This isn't happening. Control actually passes to the svc handler with the cpu in IRQ mode. I'm pretty sure this is a result of not remapping the vector table correctly. Any guidance on this?