ARM CoreSight MTB-M33 page A2-26: The MTB-M33 ensures that trace write accesses have priority over AHB accesses
1. You can setup the Core to issue an exception when it enters debug mode. It should be vector 12.
2.1/2.2: The MPU checks core bus accesses. Not DMA and not MTB.
Thank you for your reply! Now I have a better understanding of the MPU.
For bullet 1, I checked that vector12 is the Debug Monitor Handler. I enabled it in 2.1 to handle the DWT match.
But what the MTB watermark triggers is the Debug State. As Armv8-M architecture reference manual B11.4 Debug event behavior section describes, the Debug state is different from the DebugMonitor exception. The Debug state will halt the processor and only exits when the debugger clears the HALT bit or receives an external restart request, or on a warm reset.
Some operations can trigger both debug halt and debug monitor exception, such as the breakpoint, watchpoint.
I did not find any document explains that MTB WATERMARK can trigger the DebugMonitor exception. So I tried to set both the MTB WATERMARK and the DebugMonitor handler. And still cannot solve my question.
We cannot handle the debug state via the single-core, right?
Did I misunderstand the document or have the wrong tests?
Thank you again.
I think I found the solution! The MTB WATERMARK will trigger an External debug request, which can be monitored by the DebugMonitor exception! Thank you so much!