Hello everyone,
I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.
As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :
3.9.4 Error response
If a slave provides an ERROR response then the master may choose to cancel the
remaining transfers in the burst. However, this is not a strict requirement and it is also
acceptable for the master to continue the remaining transfers in the burst.
As mentioned above in the bold style : It is also acceptable for the master to continue the remaining transfers in the burst.
I have described the ERROR response from the SLAVE (hresp[1:0] = 2'b01) as shown in the figure below.
SLAVE drives ERROR response at time 75 ns with hready low. Hence MASTER detects ERROR response at 85 ns with HREADY low.
Now, if the MASTER wants to continue the current transfer; then how can it?
Can the MASTER drive address A4 (for which MASTER has received the ERROR response) at time 85 ns with SEQUENTIAL transfer (htrans[1:0] = 2'b11), though HREADY is low to continue the current transfer ?
Thanks,
So the MASTER can continue the transfer at time 85 ns without worrying about ERROR response with HREADY signal low.
Regards,
Vishal
Hello Vishal,
the ERROR response while HREADY is low is no meaning.
For the address 0x000000A6, the response at 95 ns is valid.
The MASTER can ignore the ERROR response at 95 ns and proceed the transaction of address 0x000000A8 from the time 95 ns.
Whether the SLAVE returns ERROR response or not, the MASTER should follow the HRERADY control rule.
Best regards,
Yasuhiko Koumoto.
Dear yasuhihokoumoto,
So, should the MASTER forget the 0x000000A4 address and it's related data though it is failed?
Should the MASTER also forget the 0x000000A6 address and it's related data though it is still remaining?
Can't the MASTER drive address 0x000000A6 at time 95 ns as it is still remaining ?
Best Regards,
Yes, the 0x000000A4 had not been accepted by the SLAVE.
No, the 0x000000A6 will be accepted by the SLAVE because HREADY at 95 ns (strictly speaking HREADY before at 105ns should be seen) is high.
I am sorry for the comment of "proceed the transaction of address 0x000000A8 from the time 95 ns". It was wrong.
From the 95 ns, not the 0x000000A8 but the 0x000000A6 can be taken over.
Let me excuse myself. I sometimes mistook the relationship between address and data because AHB is the pipelined transaction.
So, the MASTER can drive address 0x000000A6 at time 95 ns.