On a Cortex R, where ldm/stm are interruptible, can i use ldrex and strex for double words to pass from ISR to a task in this way?
in ISR:
STREXD, // Ignoring (yes, dumping it) if it actually failed to write , do no spin-lock or retry here at all
in Task :
LDREXD // load .. CLREX // clear exclusion
One core (2 in dual lock-step), no sharing mem with other cores. Will this work for automically write/read double words in the scenario one ISR feeding a task?
And yes, no buffering between them.
There is no general statement about the locked area, the size depends on architecture and implementation. But for what I know, it is a single bit per core. No inner/outer stuff here. Else "clrex" would not make any sense.
There is also no "nesting". Any strex clears the lock.
Edit: Typo.
42Bastian Schick
Ok, what I was referring to, prob out of scope, but this (sorry its for v7-M arch link ):
https://community.arm.com/developer/ip-products/processors/f/cortex-m-forum/10361/ldrex-strex-on-the-m3-m4-m7
... and the sub-post note in :
"
The sequence {ldrex, {ldrex, strex}, strex} should work correctly, IMO. The ldrex of the inner pair "overwrites" the effect of the ldrex of the outer pair. After the inner pair unwinds and the execution is at strex of the outer pair, it does not succeed. The outer pair runs again, hoping that the inner pair does not interfere thi ....."
see post
Having two (or more) ldrex in sequence with different addresses is IMHO an programming error. But this is by my understanding. I cannot cite any manual to "prove" this.