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Thank you for your understanding.
I use a Cortex-A7 board and write start up code.
I try to use Security Extension.
I use `smc` instruction and make cpu mode monitor mode.
In the monitor handler, I tried to changed stack pointer value for calling other functions.
But after execute `ldr sp, =_stack_start`, sp value is 0x0 (Of course, _stack_start is not 0x0 and I check it in the assembler code).
Therefore, after `push` some registers and `pop` those registers, the data abort excetpions occurred!
How can I change the sp value?
I do not use OpenOCD with my CubieBoard2, as I'm just running Linux from a SD card on this one.
Looking further into this, I'm not sure the LS1021A is supported in OpenOCD yet (eg. I do not think there's a driver for it).
To see the currently supported boards, list the contents of /usr/local/share/openocd/scripts/board/
To see the possible targets, list the contents of /usr/local/share/openocd/scripts/target/
If you feel like writing a driver for it, let me know, and I'll point you in the right direction - but it may be something that requires a fair amount of work.
Another way might be to try a differnt IDE. Which one are you using right now ?
I currentry use JLinkGDBServer and J-Link edu.
SEGGER - The Embedded Experts - Download
This supports Cortex-A7.
I checked /scripts/board directory but there are no LS1021A configure file.
I also checked other directories but there are no files for Cortex-A series.
I' m afraid that OpenOCD doesn't support this cpu.
I can't be sure, but I think Freescale's CodeWarrior might be able to debug the target.
You may want to try out the KEIL tools too.
I thought so...
From Public Git Hosting - openocd.git/tree - src/target/
History says it's been there since 2009.
Oh, and also:
from history:
For Cortex-M, a driver is needed, maybe this is not the case for Cortex-A ?
Driver? Which driver are you talking about?
Connection driver (jtag, st-link, j-link, ...)?
[EDIT]
You mean 'board driver'?
I think it's not necessary for simple debugging - when you don't need to know about things outside the processor itself
(as opposed to board, SoC or core-integrated stuff, like caches) not to mention multicore debugging.
And even then you can do that configuration if you know your system well enough.
I'm not sure, but I'd guess the above mentioned files probably have the stuff for jtag word length, commands and other
jtag configuration info.
[/EDIT]
By driver, I actually mean a chip specific driver inside OpenOCD.
For instance, OpenOCD cannot flash-program Kinetis KE devices, because a driver was not written in C for it.
Thus the Kinetis KE cannot be flash-programmed, because OpenOCD does not know how to handle or recognize it.
One cannot just use the KL driver for KE targets, because it might damage the chip if not setting the clock configuration correctly for flash-programming.
I'm not sure whether or not it can be debugged; maybe OpenOCD would actually allow debugging without knowing which device we're speaking about.
After all, it's a SWD protocol and OpenOCD knows the Cortex-A7 core. Thus a configuration file might be able to enable debugging.
Thank you for providing information.
I installed OpenOCD from the package manager, but it is the old version.
Threfore, I installed the 0.9.0-rc1 from the git repository.
I find the configuration file for Raspberry Pi 2, which has four Cortex-A7 cores.
https://gist.githubusercontent.com/jitomesky/4b564b33ef774d359d9d/raw/rpi2.cfg
I tried to connect to the board with SEGGER J-Link with this configuration file.
https://gist.github.com/garasubo/d3ff25e6617411412450
But after connecting gdb, it fails as follow:
$ sudo openocd -f ocd.cfg
Open On-Chip Debugger 0.9.0-rc1 (2015-04-27-13:13)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 1000 kHz
adapter_nsrst_delay: 400
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : J-Link V9 compiled Apr 21 2015 18:10:40
Info : J-Link caps 0xb9ff7bbf
Info : J-Link hw version 93000
Info : J-Link hw type J-Link
Info : J-Link max mem block 70896
Info : J-Link configuration
Info : USB-Address: 0x0
Info : Kickstart power on JTAG-pin 19: 0x0
Info : Vref = 1.788 TCK = 1 TDI = 0 TDO = 0 TMS = 0 SRST = 1 TRST = 1
Info : J-Link JTAG Interface ready
Info : clock speed 1000 kHz
Info : JTAG tap: ls1021a.tap tap/device found: 0xa21c64cd (mfg: 0x266, part: 0x21c6, ver: 0xa)
Warn : JTAG tap: ls1021a.tap UNEXPECTED: 0xa21c64cd (mfg: 0x266, part: 0x21c6, ver: 0xa)
Error: JTAG tap: ls1021a.tap expected 1 of 1: 0x5ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x5)
Info : JTAG tap: auto0.tap tap/device found: 0x5ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x5)
Info : JTAG tap: auto1.tap tap/device found: 0x06b0001d (mfg: 0x00e, part: 0x6b00, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x5ba00477"
Error: auto0.tap: IR capture error; saw 0x0000 not 0x0001
Warn : Bypassing JTAG setup events due to errors
Warn : Invalid ACK 0 in JTAG-DP transaction
Info : accepting 'gdb' connection on tcp/3333
Error: Register map is not available yet, the target is not fully initialised
Could you tell me how to configure for this board?
In order to dump the registers the CPU must be halted first.
Try the 'halt' command or 'reset halt', then 'reg' should work.
You should also be able to use the 'step' command after the CPU is halted.
mdw shows a 32-bit word from memory, mdh shows a 16-bit word and mdb shows an 8-bit word (byte).
mww writes a 32-bit word, mwh writes a 16-bit word and mwb writes an 8-bit word.
arm disassemble <address> <length>
should show you the disassembly.
You are not debugging on RPi2 by any chance?
In that case you need to use the GPIO pins + a boot program to switch the
multiplexed GPIO pins for that use. The two jtag-connectors are for LAN-chip and for GPU.
Even if the cores are on the same chip as the GPU, (I'm told) the cores are not in the same
scan chain with the GPU.
Yep, accessing flash, MMU, caches etc. don't work without the "board config" (=board, SoC or MCU config).
But if you know the parameters, you should be able to make a configuration that lets you debug "within the core".
If you need to upload the program with the debugger, the debugger is not of much use without the configuration (or driver).
It might be possible to "upload" a small program into RAM using MWW commands (better put them in a script; don't type them each time).
... Of course, a perl script on the host could generate an uploading script, so at least basic debugging *would* be possible; however a bit inconvenient.
I previously used SEGGER J-Link and SEGGER's gdb server to debug this board.
It works without any board specific options. I don't need to write such a special program too.
Therefore, I assume some parameters in my configuration file would be incorrect and no additional procedure such as RPi2 would be needed.
Is this of any help?
http://www.tincantools.com/wiki/OpenOCD_Troubleshooting:_JTAG_Tap_Unexpected
This may be of help too.
http://openocd.org/doc/html/Debug-Adapter-Configuration.html
This makes me think maybe you should try cmsis-dap driver.
https://community.freescale.com/thread/337734