MRS/MSR (Banked register)

Hello,

Is this instruction available in ARMv7-A, Cortex A7?

According to Cortex™-A7 MPCore™ Technical Reference Manual Revision: r0p4 (DDI 0464E), the Cortex-A7 MPCore processor supports the Virtualization Extensions (VE).

The instruction is in ARMv7VE (Virtualization Extensions) and it would be available.

There is no explanation of the M1 or M fields in ARMv7-A/R ARM, but in ARMv8 ARM there is.

The instruction encodings look the same, but what kind of mode restrictions apply?

There is the explanation.

Please refer to "Operation" description of B9.3.9 or B9.3.10.

---[snip]---
mode = CPSR.M;
if read_spsr then
  SPSRaccessValid(SYSm, mode); // Check for UNPREDICTABLE cases
  case SYSm of
    when '01110' R[d] = SPSR_fiq;
    when '10000' R[d] = SPSR_irq;
    when '10010' R[d] = SPSR_svc;
    when '10100' R[d] = SPSR_abt;
    when '10110' R[d] = SPSR_und;
    when '11100' R[d] = SPSR_mon;
    when '11110' R[d] = SPSR_hyp;
else
  BankedRegisterAccessValid(SYSm, mode); // Check for UNPREDICTABLE cases
  if SYSm<4:3> == '00' then // Access the User registers
     m = UInt(SYSm<2:0>) + 8;
    R[d] = Rmode[m,'10000'];
  elsif SYSm<4:3> == '01' then // Access the FIQ registers
    m = UInt(SYSm<2:0>) + 8;
    R[d] = Rmode[m,'10001'];
  elsif SYSm<4:3> == '11' then
    if SYSm<1> == '0' then // Access Monitor registers
      m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
      R[d] = Rmode[m,'10110'];
    else // Access Hyp registers
    if SYSm<0> == '1' then // access SP_hyp
      R[d] = Rmode[13,'11010'];
    else
      R[d] = ELR_hyp;
---[snip]---

Here,  'SYSm'  is {M:M1}  and  'm' is the register number.

It is the same description as one of ARMv8.

I guess one can't access SP_fig in user mode?

No, you cannot.

As described in ARM ARM. MRS (Banked register) or  MSR (Banked register) is UNPREDICTABLE if executed in User mode.

I believe the encoding is the same in both v7-A/R and v8?

Because the exxplanation is the same, the encoding is the same.

Best regards,

Yasuhiko Koumoto.

Hello,

Is this instruction available in ARMv7-A, Cortex A7?

According to Cortex™-A7 MPCore™ Technical Reference Manual Revision: r0p4 (DDI 0464E), the Cortex-A7 MPCore processor supports the Virtualization Extensions (VE).

The instruction is in ARMv7VE (Virtualization Extensions) and it would be available.

There is no explanation of the M1 or M fields in ARMv7-A/R ARM, but in ARMv8 ARM there is.

The instruction encodings look the same, but what kind of mode restrictions apply?

There is the explanation.

Please refer to "Operation" description of B9.3.9 or B9.3.10.

---[snip]---
mode = CPSR.M;
if read_spsr then
  SPSRaccessValid(SYSm, mode); // Check for UNPREDICTABLE cases
  case SYSm of
    when '01110' R[d] = SPSR_fiq;
    when '10000' R[d] = SPSR_irq;
    when '10010' R[d] = SPSR_svc;
    when '10100' R[d] = SPSR_abt;
    when '10110' R[d] = SPSR_und;
    when '11100' R[d] = SPSR_mon;
    when '11110' R[d] = SPSR_hyp;
else
  BankedRegisterAccessValid(SYSm, mode); // Check for UNPREDICTABLE cases
  if SYSm<4:3> == '00' then // Access the User registers
     m = UInt(SYSm<2:0>) + 8;
    R[d] = Rmode[m,'10000'];
  elsif SYSm<4:3> == '01' then // Access the FIQ registers
    m = UInt(SYSm<2:0>) + 8;
    R[d] = Rmode[m,'10001'];
  elsif SYSm<4:3> == '11' then
    if SYSm<1> == '0' then // Access Monitor registers
      m = 14 - UInt(SYSm<0>); // LR when SYSm<0> == 0, otherwise SP
      R[d] = Rmode[m,'10110'];
    else // Access Hyp registers
    if SYSm<0> == '1' then // access SP_hyp
      R[d] = Rmode[13,'11010'];
    else
      R[d] = ELR_hyp;
---[snip]---

Here,  'SYSm'  is {M:M1}  and  'm' is the register number.

It is the same description as one of ARMv8.

I guess one can't access SP_fig in user mode?

No, you cannot.

As described in ARM ARM. MRS (Banked register) or  MSR (Banked register) is UNPREDICTABLE if executed in User mode.

I believe the encoding is the same in both v7-A/R and v8?

Because the exxplanation is the same, the encoding is the same.

Best regards,

Yasuhiko Koumoto.

That made it very clear - and I also learned where the 'VE' comes from.

Arigatou gozaimasu, Yasuhiko Koumoto San.

(Nippon-jin desu ka?)

Hello. Hai, watashi wa Nippon-jin desu.

こんにちは、私は日本人です。

Yasuhiko Koumoto.

I just wasn't sure. There are a lot of people with Japanese origin that have lived all their lives in other countries, like USA.