In what situations will separate data buses ( D and S) for ARM Cortex-M4 improve performance? Also, are there any benefits of von Neuman support along with the core Harvard Architecture?
Hello,
for an execution of load or store instructions, the separate buses are beneficial.
Because of its pipeline architecture, an instruction fetch and a data access are performed at the same time.
If the buses are separated, the accesses are not interfered for each other.
However, if the instruction fetch and the data access targeted at the same memory resources, the bus collision would occur, decreasing the performance.
The situation of which performance will improve is that the instruction fetch is executed from the flash memory and the data access is targeted to the SRAM.
Regarding the benefit of von Neuman support, I cannot catch your intention of the question.
The performance of the von Neuman architecture will be smaller than non von Neuman architecture, because the instruction exists in the memory and the procedure of the fetch, decode and execution are needed compared with the direct execution of a kind of FPGAs.
Best regards,
Yasuhiko Koumoto.