General Feature of Cortex processors on cache coherency

For the Cortex-A, your choices are basically:

• Cache coherent bus
• ACP (Accelerator Coherency Port)
• Software (as in, doing it manually)

To use a Cache Coherent approach you need a processor that supports a suitable bus protocol, which for the Cortex processors means AMBA4 ACE or AMBA5 CHI.  You also need suitable interconnect fabric (such as CCI-400).  The other (non-processor) masters also need to suitable a protocol, maybe ACE-Lite.  In such a system the accesses by, for example, your DMA controller would be cache coherent with the processor(s).

ACP allows you to connect a master to the memory system through the processor.  Meaning that all its memory access pass through the processor, and so are visible to the processor's cache coherency logic.  This approach doesn't need a cache coherent bus protocol or interconnect.  For more information see:

Cortex-A9 MPCore Technical Reference Manual: 2.4. Accelerator Coherency Port

(or the TRM of the processor you plan to use)

For the Cortex-A, your choices are basically:

• Cache coherent bus
• ACP (Accelerator Coherency Port)
• Software (as in, doing it manually)

To use a Cache Coherent approach you need a processor that supports a suitable bus protocol, which for the Cortex processors means AMBA4 ACE or AMBA5 CHI.  You also need suitable interconnect fabric (such as CCI-400).  The other (non-processor) masters also need to suitable a protocol, maybe ACE-Lite.  In such a system the accesses by, for example, your DMA controller would be cache coherent with the processor(s).

ACP allows you to connect a master to the memory system through the processor.  Meaning that all its memory access pass through the processor, and so are visible to the processor's cache coherency logic.  This approach doesn't need a cache coherent bus protocol or interconnect.  For more information see:

Cortex-A9 MPCore Technical Reference Manual: 2.4. Accelerator Coherency Port

(or the TRM of the processor you plan to use)

Hi Martin,

Thanks for the reply.

How this is modeled for Cortex R and M series ?

Let us assume in case of Cortex R4 and Cortex M4 does it have the visibility outside for the AXI bus getting connected or any other special signals which denotes that ?

Regards,

Techguyz

The Cortex-R5 and Cortex-R7 both support ACP:

Cortex-R5 Technical Reference Manual: 9.8. Accelerator Coherency Port interface

ARM Cortex-R7 MPCore Technical Reference Manual: 9.7. Accelerator Coherency Port

But neither don't support ACE or CHI.

The Cortex-M processors are not my area of expertise, but I don't believe they support any cache coherency features.  But remember that Cortex-M0/1/3/4 don't have caches.