Hi Experts,
Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?
I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible to connect the DMA engine alone with processor in realization of the same or it is a special feature provided by ARM ?
Regards,
Techguyz
The Cortex-R5 and Cortex-R7 both support ACP:
Cortex-R5 Technical Reference Manual: 9.8. Accelerator Coherency Port interface
ARM Cortex-R7 MPCore Technical Reference Manual: 9.7. Accelerator Coherency Port
But neither don't support ACE or CHI.
The Cortex-M processors are not my area of expertise, but I don't believe they support any cache coherency features. But remember that Cortex-M0/1/3/4 don't have caches.