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Hi,
I'm somewhat confused with the Thumb mode code size. My understanding is compiling with ARM mode will generate 32-bit instructions and compiling with Thumb mode will generate 16-bit instructions. When I compile my Cortex-M0+ project (which should use Thumb mode instructions only), the output binary file always increments in multiple of 4 bytes. Do I miss something here?
Here are the instructions I use:
armcc -c -O3 -Ospace --cpu Cortex-M0plus --thumb --apcs=interwork -I ./ -g -c aaa.c -o aaa.o
armasm --cpu Cortex-M0plus --apcs=interwork -I ./ -g startup.s -o startup.o
armlink --cpu Cortex-M0plus --ro_base 0x00000000 --rw-base 0x00100000 --entry Reset_Handler --first __Vectors aaa.o startup.o -o aaa.axf
Thanks,
The AXF file contains a lot of other information - it's not just a raw hex file containing only the code, and different sections in it have alignment requirements the extra bits are probably just padding. If you want to get an accurate look at the size of the code use fromelf to disassemble it.
Forget to say, I'm referring the binary image size, not axf size.
fromelf --bin -o aaa.bin aaa.axf
I'd still dump out the disassembly and take a look at what it's doing - it wouldn't surprise me if the tools pad out to 4 byte multiples so the loader can use 32-bit loads.
First of all, there are at least 3 "modes" of ARM instructions - ARM, Thumb and Thumb 2. ARM indeed uses 32-bits for each instruction. Thumb indeed uses 16-bits for each instruction. However Thumb 2 uses 16-bits of 32-bits for instructions, depending on the instruction used and its variant (for example branch can use 16-bits of 32-bits). ARM Cortex-M0+ chip that you have supports most of Thumb instructions and some Thumb 2 instructions, so you cannot expect each instruction to take exactly 2 bytes. The next thing is alignment, which is usually set to 4 bytes. The last thing would be that usually instructions that load something to/from RAM store the address as a separate word in flash (because you cannot fit a full 32-bit address into a 16-bit or 32-bit instruction). Such additional words are 32-bit long (because these are addresses) and must be 32-bit aligned.
Regards,
FCh