when reading ARM® System Memory Management Unit Architecture Specification, I noticed that there is a saying in about chapter 5, the last section named <cache maintenance operations>.
In SMMUv2, client devices might perform cache maintenance operations on data and instruction caches, such as evicting data to memory.
Does this mean that SMMU are able to issue some cache coherency transactions to affect caches in ARM core platforms, through CCI for example?
If yes, how?
If no, what does it mean?
Another question is about the address translation in ARM cores platforms, will they go through SMMU too, or use their own MMUs?
I can't think of a reason to connect an A class processor via a SMMU. As you said, an A class processor has it's own MMU so it's not typically necessary. That said, I don't think there would be anything to stop you doing it.
You might connect something like a M class processor via a SMMU. For example, to allow the M class processor to access addresses greater than 32-bit.
Thanks for your reply, I am less confused now.