when reading ARM® System Memory Management Unit Architecture Specification, I noticed that there is a saying in about chapter 5, the last section named <cache maintenance operations>.
In SMMUv2, client devices might perform cache maintenance operations on data and instruction caches, such as evicting data to memory.
Does this mean that SMMU are able to issue some cache coherency transactions to affect caches in ARM core platforms, through CCI for example?
If yes, how?
If no, what does it mean?
Another question is about the address translation in ARM cores platforms, will they go through SMMU too, or use their own MMUs?
Not sure what you mean by TTB. Did you mean TBU (Translatione Buffer Unit)?
Sorry for your confusion, here I mean translation table.
Do they share one translation table or not ?
Maybe.
The SMMU can hold multiple Contexts. A context is made up of a set of translation tables, and the associated register settings.
If you have multiple masters connected to a SMMU, they could all be using the same context (and therefore the same tables). Or, they could all be using different contexts. It all depends on what they are being used for.
Which context is used is based on the StreamID. Often all the accesses from a given master will use the same StreamID. However, it's also possible that one master might use multiple StreamIDs. In which case all those StreamIDs could map to the same context, or each map to different contexts. For example, a DMA controller might support multiple concurrent jobs. You might want each job to use a different context.
Thanks a lot for your helpful explanation!