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AXI slave design and verification

Please let me know that how to design AXI slave and do its verification? If we design AXI slave using system verilog(its hdl part) then for verification what do we need to write ?I mean master would be as VIP? and How do we verify please give a general idea in steps.

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Colin Campbell over 3 years ago in reply to ash11 +1

I don't think this is a question specific to AXI, the same questions would apply about any design, so it's not something I can really help with. If you have read (and understood) the AXI spec, you know...
Colin Campbell over 3 years ago in reply to Swaniawski +1 suggested

My first reply in this thread should apply for verifying any design, not necessarily specific to AXI. For your second question, by "it" do you mean a verification environment, or their own version of...

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joanmills over 3 years ago in reply to ash11

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joanmills over 3 years ago in reply to ash11

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