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Please let me know that how to design AXI slave and do its verification? If we design AXI slave using system verilog(its hdl part) then for verification what do we need to write ?I mean master would be as VIP? and How do we verify please give a general idea in steps.
I don't think this is a question specific to AXI, the same questions would apply about any design, so it's not something I can really help with.
If you have read (and understood) the AXI spec, you know the transactions that can be performed, so test how your slave responds to those transactions, and the ones it does not support. To test the design you will need some sort of testbench, so this is something you also need to develop, and then write test vectors on that to test the bus interface on your slave, and the internal functionality, to ensure it does what you need.
None of that is anything specific to an AXI slave, it is generic design flow, so hopefully something you or your colleagues should already know how to do if you have designed RTL components before.
I am very thankful to you that you took time & replied to my question. However i haven't designed RTL components before so need step by step guide for this protocol to design and verify. I just have read the specification don't know how to initiate that for the project purpose.
Unfortunately I think what you are asking for is more than what could be covered in a forum discussion. If you are happy that you understand the protocol requirements, that's about all we could cover here.