Please let me know that how to design AXI slave and do its verification? If we design AXI slave using system verilog(its hdl part) then for verification what do we need to write ?I mean master would be as VIP? and How do we verify please give a general idea in steps.
Unfortunately I think what you are asking for is more than what could be covered in a forum discussion. If you are happy that you understand the protocol requirements, that's about all we could cover here.