Hi.I noticed that in the table of assembler instructions for the Cortex-M55 (https://developer.arm.com/documentation/101273/0001/The-Cortex-M55-Instruction-Set--Reference-Material/Cortex-M55-instructions) there are no post / pre-indexed commands for Load from memory. (LDR{type}{cond} Rt, [Rn], ±Rm {, shift} ; or LDR{type}{cond} Rt, [Rn, ±Rm {, shift}]!)Please help me if it is possible to use these instructions on the Cortex-M55?Thanks!
LDR
type
cond
Rt
Rn
Rm
shift
Yevhenii said:I would like to know if it is possible to use Load/Store register post/pre-indexing? Perhaps the instructions require certain flags to be raised now?
So you think, there are "hidden" instructions? Would be disastrous in a security focused CPU :-)