Hi.I noticed that in the table of assembler instructions for the Cortex-M55 (https://developer.arm.com/documentation/101273/0001/The-Cortex-M55-Instruction-Set--Reference-Material/Cortex-M55-instructions) there are no post / pre-indexed commands for Load from memory. (LDR{type}{cond} Rt, [Rn], ±Rm {, shift} ; or LDR{type}{cond} Rt, [Rn, ±Rm {, shift}]!)Please help me if it is possible to use these instructions on the Cortex-M55?Thanks!
LDR
type
cond
Rt
Rn
Rm
shift
All possible instructions are described in the armv8-m manuals. Do you expect some are not listed for some obscure reason? Hidden instructions?
developer.arm.com/.../LDR-and-STR--immediate-offset
Thank you very much for your reply!But I am interested in register post / pre-indexing. Referring to the command description (https://developer.arm.com/documentation/101273/0001/The-Cortex-M55-Instruction-Set--Reference-Material/Memory-access-instructions/LDR-and-STR--register-offset?lang=en&_ga=2.133969094.937322748.1619430321-560089144.1618816607) - Load instructions with pre/post-indexed register offset are not supported.I would like to know if it is possible to use Load/Store register post/pre-indexing? Perhaps the instructions require certain flags to be raised now? Or is it possible to be called differently now(not LDR...)?
Yevhenii said:I would like to know if it is possible to use Load/Store register post/pre-indexing? Perhaps the instructions require certain flags to be raised now?
So you think, there are "hidden" instructions? Would be disastrous in a security focused CPU :-)