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How to do cache invalid on Cortex-A53?

yan.wy

hi,

     I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.

     Could you give me any suggestion about cache invalid? Thanks!

     The program is:

     mov x0, #0xffff
     adr x1, label
     str x0, [x1]
     dsb sy
     isb
     ...enable MMU and D-cache
     mov x0, #0xaa55
     adr x1, label
     str x0, [x1]
     dsb sy
     isb
     bl cache_invalid_all (or use "dc ivac, x1")
     isb
     adr x1, label
     ldr x0, [x1]  ==> The "X0" value is 0xaa55, the cache invalid seems not work??

     .align 6
label:
    .quad 0
0