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Hi guys,
I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.
First consider an unaligned access on address 0x1.
Can this access be created in 2 ways?
1) Addr=0x0, Wrstrb=1110
2) Addr=0x1, Wrstrb=0111
In the second question consider an aligned access to address 0x0 with 3 incremental bursts, awsize=32-bit.
Is it possible, that only parts of these 3 accesses get written due to a strobe pattern like the following: 1011 0010 0011
Thank you in advance!
Best regards,
Martin
Hello Martin,
Mr. Dave's answer is perfect.
Can I make practical comments?
Some AXI slaves in the world cannot receive such as 'tooth-lost' write strobe other than the first and the last data.
If you want to issue such the strange strobes, you'd better to use the narrow transaction with awzie=8bit.
Even in the case, some AXI slaves in the world cannot receive such transaction as the wrstrb is all 0, although it might be against the AXI specs.
Yasuhiko Koumoto.