Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.
Register slice is described in AMBA 3.0 AXI.
"This makes possible a trade-off between cycles of latency and maximum frequency of operation."
"It is also possible to use register slices at almost any point within a given interconnect."
As you can see the first picture, register slices are located between masters and interconnect, between slaves and interconnect.
(this is a picture that i refer to any PPT about AMBA 3.0 axi.)
My questions,
Firstly, does Register slice mean the buffer???
I think that operation frequency can be increased because of operating pipelining behavior.
Secondly, where register slices is correctly located??? in masters? in the interconnect? in slaves?
I carefully guess that register slices can be located in the masters and slaves.
Because user can not modify the interconnect.
Thirdly, if i insert the register slices, where i have to design the register slices.
I want to know register slices in detail.
Hello,
Firstly, does Register slice mean the buffer??? I think that operation frequency can be increased because of operating pipelining behavior.
What do you mean by the word buffer?
It is in a sence yes and in a sence no.
The register Slice means just to re-timing AXI signals by Flip-Flops.
However, it sometimes means the AXI-AXI bridge.
Basically the interconnect is speed critical because of its many fanouts.
The register Slices are normally used in the real system.
Secondly, where register slices is correctly located??? in masters? in the interconnect? in slaves? I carefully guess that register slices can be located in the masters and slaves. Because user can not modify the interconnect.
Usually Register Slices are located between a master and an interconnect and between a slave and an interconnect.
Why do you insert the register slice? By inserting it, the latency increases.
We must avoid to insert the register slice as much as we can.
Form the system level view points, there are many things should to be considered such as Read-After-Write when we use the register slice.
Anyway, the register slice is not specifications but just only concepts to re-time the signals.
The implementation is out of the AXI specifications but it should follow the specifications.
Best regards,
Yasuhiko Koumoto.