Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.
Register slice is described in AMBA 3.0 AXI.
"This makes possible a trade-off between cycles of latency and maximum frequency of operation."
"It is also possible to use register slices at almost any point within a given interconnect."
As you can see the first picture, register slices are located between masters and interconnect, between slaves and interconnect.
(this is a picture that i refer to any PPT about AMBA 3.0 axi.)
My questions,
Firstly, does Register slice mean the buffer???
I think that operation frequency can be increased because of operating pipelining behavior.
Secondly, where register slices is correctly located??? in masters? in the interconnect? in slaves?
I carefully guess that register slices can be located in the masters and slaves.
Because user can not modify the interconnect.
Thirdly, if i insert the register slices, where i have to design the register slices.
I want to know register slices in detail.
Hi.Yasuhiko Koumoto
i wonder 3 questions.
The register Slice means just to re-timing AXI signals by Flip-Flops.
Firstly,
If i have to re-timing about signals of write address channel,
do the route of all signals of the write address channel have to add the register( as Flip-Flops) ?
What do you mean by the word buffer?
It is in a sense yes and in a sense no.
However, it sometimes means the AXI-AXI bridge.
Basically the interconnect is speed critical because of its many fanouts.
The register Slices are normally used in the real system.
Secondly,
I told "buffer" to you. It means the space which data can be temporarily saved. (as Flip-Flops)
You said "it sometimes means the AXI-AXI bridge".
I don't correctly understand that.
I want to talk to me in detail about AXI-AXI bridge.
Why do you insert the register slice? By inserting it, the latency increases.
We must avoid to insert the register slice as much as we can.
Form the system level view points, there are many things should to be considered such as Read-After-Write when we use the register slice.
Anyway, the register slice is not specifications but just only concepts to re-time the signals.
The implementation is out of the AXI specifications but it should follow the specifications.
Thirdly,
Just, I very wonder this situation. I know that the latency increases because of using register slice.
As i said before, i wonder this situation.
If i must insert the register slices, where i design the registers( as Flip-Flop ) which the signals can be passed?
From In-Gyu. Lee
Hello,
Firstly, If i have to re-timing about signals of write address channel, do the route of all signals of the write address channel have to add the register( as Flip-Flops) ?
Probably No. I think I am afraid that I could not understand your question.
Basically yes. The same direction signals (i.e. input or output) should be all re-timed.
If you intsert to the AWADDR, AWID, AWLEN, AWSIZE, AEBURST, AWLOCK, AWCACHE, AWPROT, WID. WDATA. WSTRB. WLAST. WVALID and AWALID should be also re-timed.
Secondly, I told "buffer" to you. It means the space which data can be temporarily saved. (as Flip-Flops) You said "it sometimes means the AXI-AXI bridge". I don't correctly understand that. I want to talk to me in detail about AXI-AXI bridge.
Your understanding might be wrong. The purpose of the register slice is to save the setup time and to increase speed (MHz).
AXI-AXI bridge means an AXI interconnect which have one master and one slave.
It sometimes includes more than re-timing function.
Just, I very wonder this situation. I know that the latency increases because of using register slice. As i said before, i wonder this situation. If i must insert the register slices, where i design the registers( as Flip-Flop ) which the signals can be passed?
The increase of the latency means the performance decrease.
It is not to be able to welcome it.
The best solution would be no re-timing flip-flops. It is the fastest in a performance aspect.
Actually the most timing critical signals are READY signals.
The register slices are usually inserted to release the READY signals setup timing.
If you were not familiar to STA (Static Timing Analysis), you had better not to consider about the register slice.
Best regards,
Yasuhiko Koumoto.