Hi,
I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've found, is in the Cortex-M7 reference manual as follow:
Each cache can also be configured with ECC. If ECC is implemented and enabled, then the tagsassociated with each line, and data read from the cache are checked whenever a lookup isperformed in the cache and, if possible, the data is corrected before being used in the processor.A full description of ECC error checking and correction is beyond the scope of this document.Contact ARM if you require more information.
Is there any documentation on the subject ? Would it be reported as a bus fault ? If so, which bit in the CFSR will be set ?
Thanks for your support,
David
Here is what I have concluded in my search for the answer to this (My conclusion just my judgement, not a fact)
1) The ECC on CP cache is optional on Cortex M7, that would mean it is likely chip specific.
2) STM32H7 says it supports it and it is enabled by default. You can disable it if you like.
3) There is no mechanism to expose cache ECC errors on the STM32H7. There is no bus fault or bits in a register as an indication.
Here is how I believe it behaves (STM32H7)
For Instruction Cache:
1 bit errors are corrected.
2 or more bit errors - cache line is invalidated and instruction is re-fetched from the program memory. Without Self modifying code, this is sufficient to recover.
For Data Cache:
2 or more bit errors - line is invalidated and the data is re-fetched. Any changes to cache not written to ram are lost so it is possible the re-fetched data does not properly match what the cache should have had.