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Cortex M7 cache ECC error

David

Hi, 

I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've found, is in the Cortex-M7 reference manual as follow:

Each cache can also be configured with ECC. If ECC is implemented and enabled, then the tags
associated with each line, and data read from the cache are checked whenever a lookup is
performed in the cache and, if possible, the data is corrected before being used in the processor.
A full description of ECC error checking and correction is beyond the scope of this document.
Contact ARM if you require more information. 

Is there any documentation on the subject ? Would it be reported as a bus fault ? If so, which bit in the CFSR will be set ? 

Thanks for your support,

David

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