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Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.
Firstly, i very wonder AWID, WID and BID when write transaction is started.
We assume that two masters(M0, M1-1bit ) and two slave(S0, S1) are.
The M0 master want to send the burst data to the S0 slave. the M0 master can generate the AWID( value : 0x0001 ). at that time, the M0 master must generate the WID corresponding AWID. I wonder this situation. is the WID value? simply, does the WID value have the same AWID value ( 0x0001) ? also, is the RID value? similarly, does the RID value have the same AWID value ( 0x0001) ?
Secondly, we assume that burst transaction is started.
Do WID and RID have to be generated whenever one of burst data is transferred or only one about all of the burst ?
I totally want to know about the situation.
Hello In-Gyu.Lee.
The meaning of "Write interleaving depth of 1" is that each slave can accept only one interleaved write.
Otherwise, "Write interleaving capability of 2" is a concept for a master, which might issue 2 out-standing interleaved writes,
As for the slave interfaces of the INTERCONNECT permit 1 + 1 interleave depth and the master interface to the Slave 1 of the INTERCONNECT should be permit at least 2 interleave depth.
The write interleaving depth information would be needed to design a slave which will be connected to a master of the INTERCONNECT.
Best regards,
Yasuhiko Koumoto.