Hi
I found a difference here：
In arm_cortex_m33_dgug_100235_0100_01_en page：322
[0] ENABLE Enable. SAU region enable.The possible values of this bit are:0 SAU region is enabled.1 SAU region is disabled.This bit reset to 0 on a Warm reset.
In DDI0553B_k_armv8m page：1687
ENABLE, bit [0]Enable. SAU region enable.The possible values of this bit are:0 SAU region is disabled.1 SAU region is enabled.
Which one is correct?
Sincerely
Harland
DDI0553B_k_armv8m describes the generic Armv8-M architectural behavior.
arm_cortex_m33_dgug_100235_0100_01_en describes the Cortex-M33 processor behavior.
ps: Can you point out the official Arm release web URL for arm_cortex_m33_dgug_100235_0100_01_en? Is it published by Arm?
Hi Zhifei Yang,
> ps: Can you point out the official Arm release web URL for arm_cortex_m33_dgug_100235_0100_01_en? Is it published by Arm?
This is indeed an Arm document: https://developer.arm.com/documentation/100235/latest
Best regards,
Vincent.
If this is the case, there is no page 322.in Cortex-M33 TRM.
- "In arm_cortex_m33_dgug_100235_0100_01_en page：322"
The document referred to is not the M33 TRM but rather: "Arm® Cortex®-M33 Devices, Revision: r1p0, Generic User Guide".
It does have a page 322 (4-322), which contains section "4.5.6 Security Attribution Unit Region Limit Address Register".
Thanks for your pointing out for the Cortex-M33 DGUG documeent.
To confirm now: Arm.ARM is correct while Cortex-M33 DGUG is wrong. The Cortex-M33 DGUG typo errata is recorded and will be fixed in future.
Thanks for your reply, I got the answer I wanted.