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why descriptions of SAU_RLAR is different in two user duides?

I found a difference here：

In arm_cortex_m33_dgug_100235_0100_01_en page：322

[0] ENABLE Enable. SAU region enable.
The possible values of this bit are:
0 SAU region is enabled.
1 SAU region is disabled.
This bit reset to 0 on a Warm reset.

In DDI0553B_k_armv8m page：1687

ENABLE, bit [0]
Enable. SAU region enable.
The possible values of this bit are:
0 SAU region is disabled.
1 SAU region is enabled.

Which one is correct?

Sincerely

Harland

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Zhifei Yang over 3 years ago in reply to vstehle +1 verified

Thanks for your pointing out for the Cortex-M33 DGUG documeent. To confirm now: Arm.ARM is correct while Cortex-M33 DGUG is wrong. The Cortex-M33 DGUG typo errata is recorded and will be fixed in future...

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+1 Zhifei Yang over 3 years ago in reply to vstehle

Thanks for your pointing out for the Cortex-M33 DGUG documeent.

To confirm now: Arm.ARM is correct while Cortex-M33 DGUG is wrong. The Cortex-M33 DGUG typo errata is recorded and will be fixed in future.
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+1 Zhifei Yang over 3 years ago in reply to vstehle

Thanks for your pointing out for the Cortex-M33 DGUG documeent.

To confirm now: Arm.ARM is correct while Cortex-M33 DGUG is wrong. The Cortex-M33 DGUG typo errata is recorded and will be fixed in future.
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0 Harland over 3 years ago in reply to Zhifei Yang

Thanks for your reply, I got the answer I wanted.
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