• State Not Answered
  • Locked Locked
  • Replies 1 reply
  • Subscribers 350 subscribers
  • Views 6752 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Data abort exception for unaligned access in Cortex A55

Harshit

Hi,

I have written a simple assembly code in Cortex A55, which executes in EL3, 64-bit execution state. In the code, the cache and MMU is disabled which means that any memory accessed will be treated as device memory.

There is a bit in SCTLR_EL3.A to disable the fault alignment for unaligned memory accesses. But in spite of that i am observing an exception getting triggered as Synchronous Current EL with SP_EL0”. 

                    R X0 00000000201ffed0

     166140 tic ES  (00000000000011c8:f81e401f) O el3t_s:         STUR     xzr,[x0,#-0x1c]

                    EXC [0x000] Synchronous Current EL with SP_EL0

                    ST 00000000201ffeb0 ........ ######## ######## ........    S:00201ffeb0    nGnRnE OSH

                    R ESR_EL3 0000000096000061

                    R FAR_EL3 00000000201ffeb4

                    R CPSR 800003cd

                    R SPSR_EL3 000000008000020c

                    R ELR_EL3 00000000000011c8

Can you please let me know how do i disable this without enabling the MMU ?

Thanks,

Harshit