Hi at all!
At the moment I implement the initial routines and cache-handling for Cortex-A8. All the implementation is according the Boot-Code example in Cortex-A8 Programmers Guide on page 13-4.
Now I'm a little bit confused about the handling for enabling D-side prefetch.
The code read the Auxiliary-Control-Register and set bit number 2.
MRC p15, 0, r1, c1, c0, 1 @ Read Auxiliary Control Register
ORR r1, r1, #(0x1 <<2) @ Enable D-side prefetch
MCR p15, 0, r1, c1, c0, 1 ;@ Write Auxiliary Control Register
DSB
ISB
According to the TRM on page 3-48 (3-51) bit number 2 is reserved.
Also in some other implementations of cache handling I can find these confusing handling.
Can anyone help?
Thanks,
Andreas
Hi Andreas,
The Auxiliary Control Register contains implementation specific controls so it's contents will differ between processors. The example in the Cortex-A Programmer's Guide is Cortex-A9 code, the layout of the A9's ACTLR is different from the A8 as you can see in the two TRMs:
Cortex-A9 Technical Reference Manual: 4.3.10. Auxiliary Control Register
ARM Information Center
Pete
Hi Pete,
thanks for your quick help! The mystery is solved now.