Hi guys,
I'm new to the AXI ecosystem.
However, I have one question related to unaligned read transfers.
Does AXI4 support unaligned read transfers although er are no strobe lines?
If so, which data on the bus is written?
To make it easier, discuss it on the following example:
We have a memory with address 0 to 8 with the following content:
I have a bus width of 32 bit, a burst size of 32 bit, a burst length of 1. If I read from address 0x1,
which data does the host get? Does it get the 0x44332211?
Applying a burst length of 2 to the same example. Would this then return: 0x44332211 0x88776655?
Best regards,
Martin
Hi Martin,
for the write transaction, WSTRB shows the valid byte lane of the aligned data bus.
As the data on the RDATA or WDATA, it is aligned to the bus width.
So the burst length is 1, the data on the bus is 0x44332211, and the burst length is 2, the data on the bus are 0x44332211, and 0x8877665544.
The AXI reciver (master for read, slave for write) should get it according to the address lower bits.
That is, if the address is 0x00000001, the master or slave should interrupt the data as
0x443322 for the burst length is 1 and 0x887766_55443322 for the burst lenght is 2.
Yasuhiko Koumoto.
Hi Yasuhiko,
Thanks for the answer. So it's the master's responsibility to truncate unaligned data (e.g. byte of address 0x0)?
> So the burst length is 1, the data on the bus is 0x44332211, and the burst length is 2, the data on the bus are 0x44332211, and 0x8877665544.
I assume you made a type here. The width of the second data is wider than 32-bit.
Hello Martin,
the latter is 64 bit data because the burst length is 2.
The lower 32 bit of the 2nd data is 0x55443322 and the upper 32 bit is 0x887766.
By the way, your understanding is right. For a read request, the slave only returns the data of aligned address.
64-bit data, yes. But I think you mistyped 0x8877665544 which is 40 bit.
yasuhikokoumoto wrote: By the way, your understanding is right. For a read request, the slave only returns the data of aligned address.
yasuhikokoumoto wrote:
Are the requests aligned on the bus width or on the burst size? In this example they are both the same.
If you get whole 64 bit data by an unaligned accesses, one more burst (i.e. the burst length is 3) is needed.
The requests should be aligned not on the burst size but on the bus width and only address value can be free.
Please also see AXI4: Wider transactions than BUS width allowed? .
Just to be clear on unaligned read transfer, do you mean that Slave will always return the same data i.e 0x44332211 (for burst length =1) irrespective of whether the read address issued by AXI master ix 0x0000_0000, 0x0000_0001, 0x0000_0002 or 0x0000_0003 ? Is it always the responsibility of AXI master to interpret the data properly depending on unaligned address being issued ?
Thanks,
Vishal