Hi guys,
I'm new to the AXI ecosystem.
However, I have one question related to unaligned read transfers.
Does AXI4 support unaligned read transfers although er are no strobe lines?
If so, which data on the bus is written?
To make it easier, discuss it on the following example:
We have a memory with address 0 to 8 with the following content:
I have a bus width of 32 bit, a burst size of 32 bit, a burst length of 1. If I read from address 0x1,
which data does the host get? Does it get the 0x44332211?
Applying a burst length of 2 to the same example. Would this then return: 0x44332211 0x88776655?
Best regards,
Martin
Hi Yasuhiko,
64-bit data, yes. But I think you mistyped 0x8877665544 which is 40 bit.
yasuhikokoumoto wrote: By the way, your understanding is right. For a read request, the slave only returns the data of aligned address.
yasuhikokoumoto wrote:
By the way, your understanding is right. For a read request, the slave only returns the data of aligned address.
Are the requests aligned on the bus width or on the burst size? In this example they are both the same.
Hi Martin,
If you get whole 64 bit data by an unaligned accesses, one more burst (i.e. the burst length is 3) is needed.
The requests should be aligned not on the burst size but on the bus width and only address value can be free.
Please also see AXI4: Wider transactions than BUS width allowed? .
Yasuhiko Koumoto.