ordering of memory access (Cortex M0+)

Hi all,

I have some questions regarding "memory system ordering" for Cortex M0+.

1. Does Normal memory, and Device memory really affect the system behavior?
2. If a section is "Normal memory" by default memory map, does setting the section's attributes using MPU affect the CPU's ordering of the specific section?

Ex: a Cortex M0+ MCU's peripheral register is mapped to 0x2000_0000, which by default is  specifed as "Normal memory".
          Do I need to set it's memory attributes using MPU to device memory (stongly ordered memory) specifically?

Below are some information I found in ARM's "Cortex-M0+ Devices Generic User Guide".

Section 2.2.1 mentions different default memory types/attributes.

Normal - The processor can re-order transactions for efficiency, or perform speculative reads.
Device - The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.

But in Section 4.5.9 MPU usage hints and tips, it says

In most micro controller implementations, the shareability and cache policy attributes do not affect the system behavior.

Thanks!