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Non-secure configuration of UART1 on Arm Musca-A1

Daniel Oliveira

Hi,

I'm using Arm Musca-A1 and I am stuck with the configuration of UART1 to non-secure. From my understanding, to configure the peripheral to a non-secure access setting one should configure SAU and give access to it in the 

Secure Privilege Control component (AHBNSPPCEXP0); however, after transitioning to the NS world, on the first attempt to access UART1 registers (e.g. UART1IBRD) I got an hardfault with the following status in the CFSR, HFSR and SFSR. 
Is anything that I missing? 
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  • +1 in reply to 42Bastian Schick

    On Cortex-M processors it's a little different. Nothwidstanding I was able to solve the problem. In fact I had the right assumption (you need PPC + SAU to configure a peripheral as NS), but I had some code running on Flash before I loaded my own to SRAM (which is where I am to execute). This issue is solved. 

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  • +1 in reply to 42Bastian Schick

    On Cortex-M processors it's a little different. Nothwidstanding I was able to solve the problem. In fact I had the right assumption (you need PPC + SAU to configure a peripheral as NS), but I had some code running on Flash before I loaded my own to SRAM (which is where I am to execute). This issue is solved. 

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