For any burst transfer Master has to pass only first address, for the consecutive transfer address calculation is taken care by Slave. So i want to know what is the basic difference in FIXED and INCR burst transfer?
Hello Chandan,
is your slave 1 byte width?
If it is right, the slave should get the data byte wise with incrementing the address within 4 bytes as +0, +1, +2 and +3, because the FIXED burst will issue 4 byte data (i.e. size 4) 4 times (i.e. length 4).
In such case, it would normally use so called narrow burst. That is, length 16 and size 1. However, in this case, the data alignment will be fixed at bit7-0 of the data bus.
Does this help you?
Best regards,
Yasuhiko Koumoto.
Hi Koumoto-san,
Thanks a lot for your reply. I now understand that for a salve with 1 byte width would get a narrow burst with length 16 and size 1 from master.
But I am still not able to differentiate very well between FIXED and INCR burst types.
It is mentioned in the spec as :
i) In a fixed burst, the address remains the same for every transfer in the burst.
ii) In an incrementing burst, the address for each transfer in the burst is an increment of the previous transfer address.
For every burst master would send the starting address and subsequent increments in address would be internal to slave.
Then how are these two burst types different?
Chandan
do you say about a master behavior?
If the AxSIZE is the same as bus width, they seem to be the same other than AxBUSRT. In the case of the narrow burst, the data alignment on the data bus will differ. For example, under the condition AWSIZE=1byte and the data bus width is 4bytes and the start address is 0x0, a master of the INCR burst should align data on AWDATA[7:0], AWDATA[15:8], AWDATA[23:16] and AWDATA[31:24] according to every transaction. On the other hands, a master of the FIXED busrt should put data always on AWDATA[7:0].
I think you are basically correct.I'm interested in the sentences of "Also for ARSIZE equal to bus width I feel there would be no difference from slave side also".The information which a slave can get will be the same but the interpretation of it will be implementation dependent.If the slave is a memory device such as SRAM, FIXED and INCR behavior should differ.Of course, in the case of AxLEN=0 (i.e. 1 burst), they are completely the same.
Best regards,Yasuhiko Koumoto.
If a slave would act as FIFOs, you are right.
If you are the slave designer, you can interpret the AxBURST according to your convenience.
Thanks a lot Koumoto-san.
Regards,
Thanks a lot for your helpful reply. With this example, Master behaviour is clear to me.
Similarly during read for the same example then I assume slave will reciprocate the behaviour.
That is it will put all the 4 bytes for ARLENGTH=4 bytes on ARDATA[7:0] of the bus and for INCR on RDATA[7:0], RDATA[15:8], RDATA[23:16] and RDATA[31:24].
Also for ARSIZE equal to bus width I feel there would be no difference from slave side also.
As for this same example bus width=4 bytes slave would 4 bytes for each transaction for both INCR and FIXED.
Are my assumpltions correct kindly let me know.
Thanks a lot for your kind reply.
By "Also for ARSIZE equal to bus width I feel there would be no difference from slave side also" I was meaning about the activity
seen on bus from slave side only.
Just for the sake of completion I would like to know how the implementation would differ in slave.
For INCR slave would get the starting address=0x0, for AxSIZE=4, 4 bytes of write data on the bus
and store the 4 transfers for AxLENGTH=4 by incrementing internal address to 0x4,0x8 and 0xC
and for FIXED it would store these transfer like a FIFO( for FIXED is supposed to be used for slaves like FIFOs)
But all the 4 transfers would be stored in slave for FIXED transfer also and not be overwritten.
Kindly let me know.