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Lock-Step mode execution on Cortex-R5

Ravinder

Dear Forum,

Could some one please elaborate on ,

1. what is Lock-Step Mode ?

2. What is the General HW configuration required ?

3. How to make a program/application executable in Lock-Step mode ?

- In Cortex-R5 , what are all compared at every state ? all processor registers ? what else ?

- How does processors know that, at what state they should compare results/or what ever ?
- Do the software program need to incorporate some special  lock-step instruction ? just like memory barrier instructions?

4. Please provide sample HW initialization for cortex-R5 ?

5. If lock step need some special programming in applications , please provide sample program/application to run in lock step mode?

Thanks,

Ravinder Are

Parents
  • 0 in reply to Jon Taylor

    Hi Jon,

    Thanks for your reply.

    from your reply ,

    The outputs from both cores are compared every cycle,
    1. What is the output compared here ? is it registers set ? full TCM memory ?

        Could you please elaborate the comparison happens in Cortex-R5 ?


        what is expected to be compared by  "associated comparators"  ?

       If it is a chip designer decision, what are all can be compared? what is the best thing to compare ?


    2. what is the performance impact system wide with lock-step enabling ?


    Thanks,

    Ravinder Are

Reply
  • 0 in reply to Jon Taylor

    Hi Jon,

    Thanks for your reply.

    from your reply ,

    The outputs from both cores are compared every cycle,
    1. What is the output compared here ? is it registers set ? full TCM memory ?

        Could you please elaborate the comparison happens in Cortex-R5 ?


        what is expected to be compared by  "associated comparators"  ?

       If it is a chip designer decision, what are all can be compared? what is the best thing to compare ?


    2. what is the performance impact system wide with lock-step enabling ?


    Thanks,

    Ravinder Are

Children
  • 0 in reply to Jon Taylor

    Thanks Jon for your reply, it is more useful in understanding the lock-step usage in cortex-R5.

    Regards,

    Ravinder Are

  • 0 Arm Employee Badge in reply to Ravinder

    It is the output pins of the cores that are compared - it's described in the TRM here:

    ARM Information Center

    So the effect of every instruction will be compared, every cycle. It's not the registers that are directly compared (afterall, you don't know exactly which signal or bit might be corrupted by an alpha strike - it could be logic between the registers and the output pins). The TCMs (and caches) are not duplicated as they would be protected by ECC bits. This is more efficient than having 2 copies of each memory.

    To the programmer, there is no impact on system-wide performance. The impact of using lockstep is on silicon area (which is increased as you have 2 copies of the core logic), and could potentially be on operating frequency (often decreased as it's a more complex design).

    regards,

    Jon

  • 0 in reply to Jon Taylor

    Hi Joe,

    How to test " Lock-Step " is working ?

    Please provide inputs on Testing this feature.

    Thanks,

    Ravinder Are