Dear Forum,
Could some one please elaborate on ,
1. what is Lock-Step Mode ?
2. What is the General HW configuration required ?
3. How to make a program/application executable in Lock-Step mode ?
- In Cortex-R5 , what are all compared at every state ? all processor registers ? what else ?
- How does processors know that, at what state they should compare results/or what ever ? - Do the software program need to incorporate some special lock-step instruction ? just like memory barrier instructions?
4. Please provide sample HW initialization for cortex-R5 ?
5. If lock step need some special programming in applications , please provide sample program/application to run in lock step mode?
Thanks,
Ravinder Are
Hi,
Lock-Step mode is a mode of operation used in safety critical applications. It consists of 2 copies of the Cortex-R5 logic, which are run offset a couple of cycles from each other. The idea is to protect the system from transient errors (for example a soft error caused by an alpha particle strike). The memories are protected by using ECC schemes (usually capable of detecting double bit errors, or correcting single bit errors), so both cores can reference a single memory. The outputs from both cores are compared every cycle, and if at any point they differ, an error can be signalled (this is usually unrecoverable within the system).
I'm not sure if you're a software engineer or a chip designer - if you're a software engineer, then you would need to find a device that already supports this hardware configuration (for example the Texas Instruments Hercules TMS570 series). If you're designing a new chip, then this is a design-time decision to place two copies of the core logic (along with the associated comparators).
An additional option the Cortex-R5 offers is split/lock. This has the option to select at boot time whether the two cores are run in lockstep, or split as 2 cores. This would require two copies of the memories to be placed too, to allow for "split" operation. Again, the option to have a split/lock processor is decided on when the device is designed.
To a programmer, this process is transparent. No special coding is needed and the comparison between locked core happens automatically.
If you can provide some more details about your particular application/use case I may be able to give a more specific answer.
regards,
Jon
Hi Jon,
Thanks for your reply.
from your reply ,
The outputs from both cores are compared every cycle, 1. What is the output compared here ? is it registers set ? full TCM memory ?
Could you please elaborate the comparison happens in Cortex-R5 ?
what is expected to be compared by "associated comparators" ?
If it is a chip designer decision, what are all can be compared? what is the best thing to compare ?
2. what is the performance impact system wide with lock-step enabling ?
Thanks Jon for your reply, it is more useful in understanding the lock-step usage in cortex-R5.
Regards,
It is the output pins of the cores that are compared - it's described in the TRM here:
ARM Information Center
So the effect of every instruction will be compared, every cycle. It's not the registers that are directly compared (afterall, you don't know exactly which signal or bit might be corrupted by an alpha strike - it could be logic between the registers and the output pins). The TCMs (and caches) are not duplicated as they would be protected by ECC bits. This is more efficient than having 2 copies of each memory.
To the programmer, there is no impact on system-wide performance. The impact of using lockstep is on silicon area (which is increased as you have 2 copies of the core logic), and could potentially be on operating frequency (often decreased as it's a more complex design).
Hi Joe,
How to test " Lock-Step " is working ?
Please provide inputs on Testing this feature.