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Cache cleaning and invalidating in ARM Cortex-A

Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two discrete steps. If another core were to access the affected address between those two actions, a coherency problem can occur. Such problems can be avoided by following two simple rules.

• When cleaning, always clean the innermost (L1) cache first and then clean the outer cache(s).

• When invalidating, always invalidate the outermost cache first and the L1 cache last.

So is the below mentioned order proper ?

when Cleaning the cache L1 : it should be as Clean L1

when Cleaning the cache L2 : it should be as Clean L1, then clean L2.

When invalidating the Cache L1 : Clean L1, L2, Invalidate L2, L1

When invalidating the Cache L2 : Clean L1, L2, Invalidate L2

Please correct me if im wrong.

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