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8-byte stack alignment for ARM Cortex-A9

Holger Elsenheimer

Hello everbody,


as i have written before in "Compability between architecture ARMv5TE and ARMv7-A", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our risk disclosure ist the stack alignment.

Our Customers have own IEC 61131 Code in compiled form, that cannot be changed. This code can call external functions from our OS, unfortunately with a stackptr, which is not 8-byte aligned. Rarely, but it can happen.

So I've read the support article "Eight-byte Stack Alignment" in the ARM Information Center, where I found the following sentences:

"...Eight-byte stack alignment is of particular benefit to processors supporting LDRD and STRD instructions, for example, processors based on ARM architecture v5TE

and later. If the stack is not eight-byte aligned the use of LDRD and STRD might cause an alignment fault, depending on the target and configuration used"

My questions:

- Are there other instructions besides LDRD and STRD, that can make problems with a NOT 8-byte aligned Pointer? We could scan our externally callable functions for this instructions.

- Is there any support from the processor to handle or correct a misaligned stack pointer, except a manipulation by inline assembler? (I've read about STKALIGN in the ARM Cortex-M processor family)

Thanks und best Regards,

      H.Elsenh.

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    In ARMv7-A, the alignment requirement for LDRD/STRD is 4-byte.  There is potentially a performance benefit if the address is 8-byte aligned.  In ARMv5TE they were required to 8-byte aligned.

    More generally, I suspect the problem you'd hit is other code making assumptions about the stack pointer. For example when manipulating the stack pointer.  If their starting assumption (SP is 8-byte aligned) is wrong, then the manipulation might go wrong.

    Could you put some kind of veneer between the old code and the OS?

    NOTE: There are some instructions which do require 8-byte alignment, such LDREXD. You can find details of the alignment needed for different load/store instructions in section A3.2.1 (Unaligned data access) of the ARMv7-A/R Architecture Reference Manual (C.c)

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    In ARMv7-A, the alignment requirement for LDRD/STRD is 4-byte.  There is potentially a performance benefit if the address is 8-byte aligned.  In ARMv5TE they were required to 8-byte aligned.

    More generally, I suspect the problem you'd hit is other code making assumptions about the stack pointer. For example when manipulating the stack pointer.  If their starting assumption (SP is 8-byte aligned) is wrong, then the manipulation might go wrong.

    Could you put some kind of veneer between the old code and the OS?

    NOTE: There are some instructions which do require 8-byte alignment, such LDREXD. You can find details of the alignment needed for different load/store instructions in section A3.2.1 (Unaligned data access) of the ARMv7-A/R Architecture Reference Manual (C.c)

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