Hi,
I am working with GICV3 on a Cortex A53 that is currently in aarcH32 EL2 state.
When I try to read the ICC_HSRE I get an undefined instruction and the system crashes.
The instruction I am using is
mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
mrc p15, 4, r7, c12, c9, 5
@ ICC_HSRE
Any idea what is wrong here, and why I get an undefined instruction.
In aarch32 EL2, I am pretty sure this is the register that should be used to access the GIC System Register Enable Register?
Ok. So are you saying I need to switch to EL3 first to be able to set the ICC_MSRE.Enable bit?
And then from that point on I should be able to access ICC_HSRE?
You are starting up in EL3, so you should there enable set the rights for EL2..EL0.
Bastian, this issue is showing up again. When I start up in EL3 (on i.MX8M) it seems I cannot access ICC_SRE_EL2.
If I put the following instruction in to my code I get a crash
mrs x8, s3_4_c12_c9_5
I believe this to be the correct mnemonic to access ICC_SRE_EL2.
I've looked at this every way I can but find a way to make it work. Any ideas?