NVIC_EnableIRQ : enables only one interrupt at a time?

Thanks for answering. However, my question is more about the purpose of use of the register, rather than how to use it.

In fact, Id be glad to know the answer, if setting an  IER register of a peripheral device will be ok, without enabling its interrupt over the ISER (as descrbied in my second question below) ?

Thanks for answering. However, my question is more about the purpose of use of the register, rather than how to use it.

In fact, Id be glad to know the answer, if setting an  IER register of a peripheral device will be ok, without enabling its interrupt over the ISER (as descrbied in my second question below) ?

I am confused: You are asking of the purpose of the ICER and ISER?

2nd question: You need to enable the interrupt in both the peripheral _and_ the NVIC to get interrupted.
Only peripheral will mean NVIC lists the interrupt as pending (so you can poll it).
Only NVIC is useless.

1) No, ICER not at all. Only about the relationship between the ISER and the IER.

2) You are saying: It is need to both Enable NVIC->ISER and UART->IER simultaneously ?

The source of confusion is the source code of enabling the NVIC IRQ

static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}

If I want to enable multiple IRQs over UART->IER simultaneously, I have to do the following ?

NVIC_EnableIRQ(UART3_IRQn);

PC_UART3->IER = ...

NVIC_EnableIRQ(UART2_IRQn);    // this disables UART3 already

PC_UART2->IER = ...

So, what happens with the NVIC UART3_IRQn respectively with the PC_UART3->IER, if the NVIC_EnableIRQ(UART2_IRQn) disables the UART3_IRQn? Do I have to poll the UART3->IER than?

Why is this connection not specified / stated clearly in the specification ?

ISER/ICER : Atomically set/clear bits. You can of course set/clear more then one bit. But not with the CMSIS function but by directly writing.
NVIC->ICER = 0xffffffff; /* clear all interrupts */

And no "NVIC_EnableIRQ(UART2_IRQn);    // this disables UART3 already" is wrong. Hence the name is "ISER". It does only set those bits are written one. It does _not_ clear those where you write a zero.

Also, you mix core (NVIC) and peripheral/SoC (UART). The core/NVIC has several input lines. These are connected to the SoC peripherals (UART or GPIO or ...).

Since the NVIC does not know about the peripheral you have to enable interrupts at the source (peripheral) and the sink (NVIC).

Look at the source code

NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));

it does clear the bits, which had been written to one.

I know this, but its about the purpose of the source code -> NVIC_EnableIRQ, which does set only one bit at a time ...

So, do I have to set it manually, i.e. by my own, i.e. not using NVIC_EnableIRQ, but setting ISER directly ?

42Bastian Schick said:

ISER/ICER : Atomically set/clear bits. You can of course set/clear more then one bit. But not with the CMSIS function but by directly writing.
NVIC->ICER = 0xffffffff; /* clear all interrupts */

As I wrote before. Yes!

Thanks, I didnt understand it that clearly.

Where in the specification can I read about this relationship, i.e. why the spec doesnt say anything about it ?

Which spec are you talking about. The TRM is clear about it.

Could you pelse refer to the place in the TRM spec ?

See above: Chapter B3.4.4 Armv7-M:DDI0403E_d

This chapter is about the ISER, but still no relationship between the ISER and IER...

Again: NVIC => Core, UART => SoC, so read the manual for the SoC you are using.

In the SoC manual, there is no reference about such relationship ...

Do you have an example SoC spec where such relationship is specified ?

STM32F4:

It all is clearly written, but sometimes, not at one place. I suggest getting a copy of "The definitive guide to Arm Cortex-M3 and_cortex_m"