NVIC_EnableIRQ : enables only one interrupt at a time?

ISER/ICER : Atomically set/clear bits. You can of course set/clear more then one bit. But not with the CMSIS function but by directly writing.
NVIC->ICER = 0xffffffff; /* clear all interrupts */

And no "NVIC_EnableIRQ(UART2_IRQn);    // this disables UART3 already" is wrong. Hence the name is "ISER". It does only set those bits are written one. It does _not_ clear those where you write a zero.

Also, you mix core (NVIC) and peripheral/SoC (UART). The core/NVIC has several input lines. These are connected to the SoC peripherals (UART or GPIO or ...).

Since the NVIC does not know about the peripheral you have to enable interrupts at the source (peripheral) and the sink (NVIC).

ISER/ICER : Atomically set/clear bits. You can of course set/clear more then one bit. But not with the CMSIS function but by directly writing.
NVIC->ICER = 0xffffffff; /* clear all interrupts */

And no "NVIC_EnableIRQ(UART2_IRQn);    // this disables UART3 already" is wrong. Hence the name is "ISER". It does only set those bits are written one. It does _not_ clear those where you write a zero.

Also, you mix core (NVIC) and peripheral/SoC (UART). The core/NVIC has several input lines. These are connected to the SoC peripherals (UART or GPIO or ...).

Since the NVIC does not know about the peripheral you have to enable interrupts at the source (peripheral) and the sink (NVIC).

Look at the source code

NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));

it does clear the bits, which had been written to one.

I know this, but its about the purpose of the source code -> NVIC_EnableIRQ, which does set only one bit at a time ...

So, do I have to set it manually, i.e. by my own, i.e. not using NVIC_EnableIRQ, but setting ISER directly ?

42Bastian Schick said:

ISER/ICER : Atomically set/clear bits. You can of course set/clear more then one bit. But not with the CMSIS function but by directly writing.
NVIC->ICER = 0xffffffff; /* clear all interrupts */

As I wrote before. Yes!

Thanks, I didnt understand it that clearly.

Where in the specification can I read about this relationship, i.e. why the spec doesnt say anything about it ?

Which spec are you talking about. The TRM is clear about it.

Could you pelse refer to the place in the TRM spec ?

See above: Chapter B3.4.4 Armv7-M:DDI0403E_d

This chapter is about the ISER, but still no relationship between the ISER and IER...

Again: NVIC => Core, UART => SoC, so read the manual for the SoC you are using.

In the SoC manual, there is no reference about such relationship ...

Do you have an example SoC spec where such relationship is specified ?

STM32F4:

It all is clearly written, but sometimes, not at one place. I suggest getting a copy of "The definitive guide to Arm Cortex-M3 and_cortex_m"

42Bastian Schick said:

I suggest getting a copy of "The definitive guide to Arm Cortex-M3 and_cortex_m"

Absolutely!

https://www.elsevier.com/books/the-definitive-guide-to-arm-cortex-m3-and-cortex-m4-processors/yiu/978-0-12-408082-9

You mean the sentence "All interrupts are managed by the NVIC" gives the relationship between the ISER and the IER ?

PS btw is the exert from a SoC manual?

As in every system and SoC I have seen so far in the last 35 years, you have to enable interrupt generation in the peripheral (IER in your case) and in the interrupt controller (NVIC here).

And yes, it is from the SoC manual, hence the "STM32F4" at the top.