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Program Counter, Stack Pointer and Link Register Status During an Interrupt Service in ARM based Processors

what happens when interrupt comes to program counter stck pointer and link register in ARM based Processor Architeture ?

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  • Which processor?

    For Armv7-A and earlier, assuming the exception is taken:

    • The PC will be set to the appropriate exception vector
    • SPSR_<mode> will be set to the CPSR value immediately before the exception
    • CPSR will be update with the correct mode and instruction set.
    • LR_<mode> will be set to the exception return address
    • SP will now select SP_<mode>
    Where <mode> is the exception mode.  So for an interrupt, it would be SPSR_irq, LR_irp and SP_irq.
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  • Which processor?

    For Armv7-A and earlier, assuming the exception is taken:

    • The PC will be set to the appropriate exception vector
    • SPSR_<mode> will be set to the CPSR value immediately before the exception
    • CPSR will be update with the correct mode and instruction set.
    • LR_<mode> will be set to the exception return address
    • SP will now select SP_<mode>
    Where <mode> is the exception mode.  So for an interrupt, it would be SPSR_irq, LR_irp and SP_irq.
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  • Thanks Martin,

    I wanted to know generally what happens with the processors when interrupt arrived and how the r13 r14 and r15 reacts to that  I was looking for the answer and still its helpful what you have written 

    and this is about basic ARM Based Processor Architecture i was asking for

    Thanks again

     .

    It's still helpful and please if you explain more that's also helpful.