Hi,
I would like to know the interrupt behavior on Out-of-Order pipeline on Cortex-A15.
When some instruction is executing on Out-of-Order pipeline, one interrupt is happens.
In this case, its interrupt must wait until finish the current executing instruction?
If it is yes, it makes long wait for interrupt.
For example,
If a load instruction with PCIe transaction is executing on pipeline, the interrupt may wait long time until the load instruction finished.
I think this situation make the performance decreasing dramatically.
Does Cortex-A15 core have some feature for protecting this situation?
I appreciate your quick reply.
Best regards,
Michi
I think you are confusing what is architecturally guaranteed with the way a particular implementation might behave. The architecture says that interrupts arte taken following completion of the instruction. But that is only defined at a local level. It would not, to use your example, take into account whether an outstanding PCIe transaction had completed. That is beyond the scope of the architecture and outside the knowledge of the pipeline at a local level.
Chris
Dear Chris-san,
Thank you for your advice.
But I am still confusing.
You said that A15 core does not wait that PCIe transaction had completed. It is an outstanding at a local level.
Regarding "local level", you said, it does not include the completion time that for "load" instruction to memory space assigned to PCIe,
I don't know why load(or store) instruction is outstanding at local level. If the load instruction to memory space assigned to DDR3, isn't it outstanding?
Please advise me again.