Hi,
I would like to know the interrupt behavior on Out-of-Order pipeline on Cortex-A15.
When some instruction is executing on Out-of-Order pipeline, one interrupt is happens.
In this case, its interrupt must wait until finish the current executing instruction?
If it is yes, it makes long wait for interrupt.
For example,
If a load instruction with PCIe transaction is executing on pipeline, the interrupt may wait long time until the load instruction finished.
I think this situation make the performance decreasing dramatically.
Does Cortex-A15 core have some feature for protecting this situation?
I appreciate your quick reply.
Best regards,
Michi
> I think this situation make the performance decreasing dramatically.
Why do you think this is any worse than running interrupt handlers themselves? Most interrupt handling on a A-profile CPU will result in multiple cache misses, TLB misses, and typically will itself talk to peripherals over some peripheral bus interface. One or two pending loads is unlikely to significantly impact performance.
A-profile software typically isn't _that_ sensitive to interrupt latency (on a "big OS" such as Linux you typically have many thousands of cycles of kernel overheads before you even get to the interrupt handler in the device driver, and most "real work" is deferred to a work queue which waits on a kernel thread reschedule which may take thousands more cycles before it is scheduled if the system is busy).
HTH,
Pete
Dear Peter-san,
Thank you for your email. I appreciate your support.
May I ask one more question again?
Please see the below picture.
I would like to know which area existing instructions are discarded. When an interrupt occurs, some instructions on Out-of-Order pipeline ( I marked it as No.6 stage) is completed? After all instructions on No.6 stage are completed, does the interrupt jump to handler?
Or only some instructions on No.7 stage (it is very close to the Retirement buffer, but it does not enter to the retirement buffer yet.) are completed before the interrupt jumps to the handler. And all instructions on No.6 stage are discarded before the interrupt?
Please advise me again.
This is internal implementation detail of the CPU not programmer's model - we don't disclose this level of detail publically,sorry.