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Hello,
Regarding AXI WR transaction.
I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid.
This means that in order to complete the transaction, sometimes in the future the matching address cahnnel id is put on the AXI adress channel lines.
Is it a must that no other write transaction with the same id will enter in the mid of that transaction?
Thank you.
Hi Rakesh,
>Q) In AXI4 WID, signal is not supported right.
Yes, right. AXI4 has removed the support for write data interleaving, so all WDATA are strictly in order with respect to AW.
>How could bus matrix recognise the ID of early WDATA to generate the corresponding AWID and complete the transaction.?
An AXI4 bus matrix would just associate the early WDATA with the next incoming AW command, because in AXI4 the master is guaranteed to generate fully in order AW and W.
Regards,
Xingguang