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Hello,
Regarding AXI WR transaction.
I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid.
This means that in order to complete the transaction, sometimes in the future the matching address cahnnel id is put on the AXI adress channel lines.
Is it a must that no other write transaction with the same id will enter in the mid of that transaction?
Thank you.
>I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid.
I would expect the bus matrix to hold the early WDATA in an internal buffer (if any) without routing it to any destination, because it does not know the destination yet. After some time, when the AW information arrives, it can then perform data routing as normal. If the bus matrix does not have sufficient buffer to hold the WDATA, it would drive the WREADY signal low to stall the W channel.
In general, I would expect an AXI master to issue AW before W, or AW and W at the same time. However, due to different number of delay elements (e.g. register slice) on each channel, the bus matrix may see WDATA before AW command.
>This means that in order to complete the transaction, sometimes in the future the matching address cahnnel id is put on the AXI adress channel lines.
Yes.
>Is it a must that no other write transaction with the same id will enter in the mid of that transaction?
The AXI ordering rules must be obeyed in any case. The AXI protocol requires that the first piece of WDATA must be issued in the same order as the AW address. That means, if the bus matrix first sees an early WDATA with WID=x, then the future AW command must have AWID=x (otherwise, protocol violation) and would be assumed to be related to that WDATA.
Regards,
Xingguang
Hi.,
>> if the bus matrix first sees an early WDATA with WID=x, then the future AW command must have AWID=x (otherwise, protocol violation) and would be assumed to be related to that WDATA.
Q) In AXI4 WID, signal is not supported right. How could bus matrix recognise the ID of early WDATA to generate the corresponding AWID and complete the transaction.?
Thanks,
Rakesh.
Hi Rakesh,
>Q) In AXI4 WID, signal is not supported right.
Yes, right. AXI4 has removed the support for write data interleaving, so all WDATA are strictly in order with respect to AW.
>How could bus matrix recognise the ID of early WDATA to generate the corresponding AWID and complete the transaction.?
An AXI4 bus matrix would just associate the early WDATA with the next incoming AW command, because in AXI4 the master is guaranteed to generate fully in order AW and W.
Thank you. Now I am clear on this.