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Hello,
I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes) is the trasaction splitted into 2 cache lines (2X64byte)? Thanks
Hanan