Hi,
This question is regarding Cortex-A15 L2ACTLR[27] bit ("Force L2 logic clock enable active"). If the clock to L2 block has to be forced to be active all the time (L2ACTLR[27] = 1), is it sufficient if one of the A15 Cores in the MPCore setting this bit? Or does all the four CPUs in the A15 MPcore need to set this bit?
Thanks,
Thomas.
based on my understanding:
L2 Cache is shared by all cores in a cluster.
So, only BSP set it is enough!
Hi Chinatiger,
Thanks for talking a look. But the question was more about how many A15 CPUs in a Quad A15 MPCore should set the ACTLR[27] bit?
Is it correct to say that, if any one of the A15 CPU in a Quad A15 MPCore sets ACTLR[27] bit is sufficient to disable the L2 auto clock gating feature?
hi, Thomas:
I think yes!